1. Field of the Invention
The present invention relates to a polishing apparatus, and more particularly to a polishing apparatus for polishing a workpiece such as a semiconductor wafer to a flat mirror finish.
2. Description of the Related Art
Recent rapid progress in semiconductor device integration demands smaller and smaller wiring patterns or interconnections and also narrower spaces between interconnections which connect active areas. One of the processes available for forming such interconnection is photolithography. Though the photolithographic process can form interconnections that are at most 0.5 μm wide, it requires that surfaces on which pattern images are to be focused by a stepper be as flat as possible because the depth of focus of the optical system is relatively small.
It is therefore necessary to make the surfaces of semiconductor wafers flat for photolithography. One customary way of flattening the surfaces of semiconductor wafers is to polish them by a chemical mechanical polishing (CMP). The chemical mechanical polishing is performed by pressing a semiconductor wafer held by a carrier against a polishing cloth mounted on a turntable while supplying an abrasive liquid containing abrasive grains or material onto the polishing cloth.
For polishing a compound semiconductor or the like, two different abrasive liquids are supplied in two stages to polish the compound semiconductor. For example, U.S. Pat. No. 4,141,180 and Japanese laid-open patent publication No. 4-334025 disclose polishing apparatuses for polishing a compound semiconductor, respectively. Each of the disclosed polishing apparatuses has two turntables. A carrier which holds a semiconductor wafer is moved between the turntables, for polishing the semiconductor wafer by means of a two-stage polishing comprising a primary polishing and a secondary polishing on the respective turntables and cleaning the semiconductor wafer between the two-stage polishing. In the cleaning process, the lower surface, which has been polished, of the semiconductor wafer is cleaned by water and/or a brush.
The conventional polishing apparatuses have suffered the following problems:
(1) Since the cleaning process which is carried out between the primary polishing and the secondary polishing is effected in such a state that the semiconductor wafer is being attached to the carrier, upper and side surfaces of the semiconductor wafer cannot be cleaned. The abrasive liquid containing abrasive grains which has been used in the primary polishing and remained on the upper and side surfaces of the semiconductor wafer serves as a pollution source in the secondary polishing, thus lowering quality of the polished semiconductor wafer.
(2) In the polishing apparatus disclosed in U.S. Pat. No. 4,141,180, since the two turntables are positioned closely to each other, the abrasive liquid on one of the turntables reaches the other of the turntables and tends to contaminate the semiconductor wafer when it is polished on the other of the turntable.
(3) Some workpieces such as silicon wafers are not required to be polished in the two-stage polishing. Since the polishing apparatus has only a single carrier in U.S. Pat. No. 4,141,180, both the turntables cannot be simultaneously operated for increasing the throughput of the workpieces that can be processed by the polishing apparatus. The polishing apparatus disclosed in Japanese laid-open patent publication No. 4-334025 has two carriers that move on the same rail between two of the turntables and the cleaning unit. Even if one of the carriers finishes a polishing operation, it has to wait until the other carrier finishes its polishing operation. Therefore, the efficiency of operation of the carriers is relatively low, adversely affecting the throughput and the quality of semiconductor wafers which have been polished.